Intel: Compiler Engineering Intern

I’m interning at Intel in San Jose, CA, through January 2027, on the PTA (Performance, Tools, and Analysis) team on the oneAPI compiler org. The job is basically: find headroom in the icx compiler across C/C++/Fortran workloads, and then go get it.

Day to day, that means running perf and VTune over a bunch of real workloads — SEAL (homomorphic encryption), LLVM and CPython builds, zstd, discrete-event network simulators, an EDA chip-design tool — chasing a regression down until it’s a minimal repro. Once I’ve got that, I’m actually in the compiler: writing and patching optimization and simplification passes, debugging why auto-vectorization decided not to fire, and tuning inlining and loop unrolling until the generated code actually uses the cache and the SIMD units the way it should. I found and fixed a hardware-level TLB-miss regression that only showed up once generated code hit real memory-access patterns, and wrote a new vectorization pass for a specialized search-loop shape plus hand-vectorized NTT/inverse-NTT kernels, which pushed throughput on the affected benchmarks up by around 10%.

A lot of the actual hours are spent reading vectorized x86 output side by side with source and IR, trying to close the gap between what the compiler could theoretically emit and what it actually does.

Most of my compiler experience before this was academic — building compilers for coursework targeting x86-64. Working inside a production toolchain at this scale is different: the distance between a missed vectorization and a measurable performance regression is very short, and that’s exactly the kind of environment I wanted to be in.